Astera Labs is seeking an Analog / Mixed-Signal Layout Engineer in Singapore to join its ASIC team. The role focuses on design and verification of high-performance computing systems utilizing advanced CMOS technology. The ideal candidate should be pursuing a BS or MS in EE/CS, with hands-on knowledge of RTL design languages like Verilog/System Verilog and familiarity with verification methodologies. Exposure to high-speed interfaces such as PCIe and DDR is preferred. The company promotes diversity and encourages applicants from all backgrounds.
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