Job Description

We are looking for highly skilled and efficient Design Verification engineers to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using industry proven constrained random methodologies with System Verilog and UVM. You will become a member of an extremely skilled and efficient group of engineers working on PCIe and other host interfaces. The technology is constantly evolving and this provides a chance to work on leading edge technology that is also used in other product lines. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Skills

• Self motivated personality with a strong presence to do things right
• Strong sense of teamwork and ability to work well with others
• Constrained random verification methodologies with experience driving completion via coverage closure
• Preferable to have skills with SV and UVM, ...