Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.
Perform functional verification of SERDES blocks, including TX/RX data paths, equalization algorithms, adaptation loops, CDR behavior, PLL locking, and analog/digital interactions.
Debug and resolve simulation failures across analog, digital, and mixed-signal domains, ensuring root-cause analysis and timely solutions.
Conduct design reliability checks such as electromigration (EM), IR analysis, and device-level stress evaluations to ensure silicon robustness.
Collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP. <...
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