Utilize commercial and in‑house EDA tools (Synopsys, Cadence, Siemens) for the design and implementation of 100–400million gate integrated circuits across 7nm, 5nm, 3nm, 2nm process technologies. Handle full RTL‑to‑GDS or Gates‑to‑GDS flow, including Placement, clock tree synthesis, detailed routing, physical verification, formal verification, and timing analysis. Knowledge of front‑end design and synthesis is advantageous.

Degree, Master’s or PhD in Electrical, Electronics, or Computer Engineering. Minimum five years or more of relevant experience. Proficiency in UNIX/Linux and scripting languages (e.g., TCL, Bash). Familiarity with front‑end design tools is a plus.

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