ASIC RTL Design Engineer
Location:

Bengaluru, India
Experience:

5–10 Years
Role Summary
We are looking for a highly skilled

ASIC RTL Design Engineer

to design and develop high-performance PCI Express (PCIe) IPs and SoC components. The ideal candidate will have strong expertise in microarchitecture definition, RTL design, and implementation of high-speed digital logic for next-generation semiconductor products.
Key Responsibilities
Design and implement RTL for PCI Express (PCIe) controllers, subsystems, and high-speed digital IPs.
Translate architecture specifications into efficient microarchitecture and high-quality RTL.
Develop scalable, high-performance, and low-power digital designs using Verilog/SystemVerilog.
Perform functional analysis, logic optimization, lint, CDC, and synthesis-ready RTL development.
Collaborate with Architecture, Verification, Physical Design, DFT, and Firmware teams throughout the development ...