Role Description

Key Responsibilities

• RTL-to-GDSII Implementation: Own the entire physical design flow, from netlist to final GDSII delivery.
• Floorplanning & Partitioning: Define chip area, I/O placement, and layout constraints.
• Placement & Routing (PnR): Place standard cells and route wires using EDA tools (e.g., Cadence Innovus, Synopsys Fusion Compiler).
• Clock Tree Synthesis (CTS): Design the clock distribution network to meet timing and skew requirements.
• Physical Verification: Ensure layout adheres to design rules (DRC) and matches the schematic (LVS), along with antenna checks.
• Timing Closure & Optimization: Perform Static Timing Analysis (STA) and optimize for performance and power (PPA).
• Power & Reliability Analysis: Design power delivery networks (PDN) and check for IR drop/Electromigration (EM).

Required Skills and Qualifications

• Education: Bachelor’s or M...