Join Astera Labs as a Verification Engineer and apply your expertise in C/C++ and UVM to improve cutting-edge AI infrastructure solutions. Your role will focus on enhancing verification processes for SoC products.

We are seeking a Principal Design Verification Engineer with over eight years of experience in complex silicon product development. You must be adept in UVM and System Verilog environments while employing high-level programming languages for RTL simulation and emulation. Your professional experience will enable you to prioritize multiple tasks effectively and work collaboratively with minimal guidance.

Key Responsibilities:
• Integrate C/C++ in System Verilog using DPI/PLI
• Develop and execute UVM-based test plans
• Utilize scripting tools to automate processes
• Work independently with RTL designers on debugging
• Implement transaction-based verification methods

Requirements:
• Bachelor’s in Electric...