Job Description1. Memory subsystem (memory controller, system cache) and interconnect (on-chip and cross-chip) architecture design for Smart Phone, Automotive, High-performance Computing, or Data Center
2. System-level SW/HW behavioral power/performance analysis/optimization focusing on interplays between compute system (CPU/GPU/NPU/DSP/etc.) and memory system
3. Memory subsystem performance/power profiling, modeling, and competitive analysisRequirementMinimum qualifications:
1. Master's degree in Electrical Engineering or Computer Science or equivalent practical experience
2. Experience using SystemC/Verilog/VHDL or C/C++/Python
3. Knowledge of cache, memory, interconnect background, system design, and modeling tools

Preferred qualifications:
1. Experience with architectural design/optimization of memory hierarchy (including SRAM and LPDDR/GDDR/HBM) or interconnect (NoC, PCIe, etc.) is a plus.
2. Experience with performance/power profiling in using...