Job Title: DFT Engineer Location: San Jose CA (Day-1 Onsite) Duration: 12 Months Experience: 10 yrs Note: Seeking DFT Engineer with ATPG and Scan experience
Key Responsibilities:
DFT implementation, including Scan, ATPG, Sims, Post-Si diagnosis at block and SoC level
Verify test patterns using gate-level simulations.
Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.
Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing.
Synopsys TetraMax, VCS, Verdi and DC/Fusion compiler work experience is must.
Preferred Qualification:
Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG.
Proven experience in developing DFT specifications and architectures for complex designs.
Expertise in debugging DFT issues, inc...
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