Undertake the role of layout engineer for day-to-day project execution of a variety of layout design implementation, including but not limited to Foundation IP (IO/ESD), Analog IP and RFIC, across multiple process nodes and diversified foundries.
Collaborate with process-oriented or project-oriented multi-functional teams in delivering the physical design portion of IP, test-chip, RFIC or SoC.
Be the DRI (Directly Responsible Individual) for the tasks assigned and assume full responsibility of the complete layout implementation process, including floor planning layout construction, physical verification and QA flow sign-off.
Provide timely project status updates and proactively anticipate and mitigate potential execution pitfalls to ensure smooth and high-quality delivery for each project.
Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power,...
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