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Design Verification Engineer

Company

Tessolve Semiconductor Private Limited

Location

Bengaluru, Karnataka

Posted

June 02, 2026

Position Overview

- IP verification Using SV/UVM - SOC Verification using C/SV - Third Party VIP Integration - Interconnect Protocols: AHB, AXI, APB - SOC Interfaces: GPIO, SPI, I2C, UART (4+) - High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) - Memory Interfaces: DDR or HBM I/O (10+) - Coverage Closure: Code, Functional and Toggle - Tools: Synopsys VCS or Cadence Incsive - Technical Documentation: Testbench Specification, Test Plan Specification - Foundry Porting Experience: Technology Library Conversion Related Changes Verification

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