Experience: 5 Years
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics

Roles and Responsibilities

Verilog, System verilog, UVM
VHDL, UVVM
Simulator exposure with VCS, Questa, Xcelium
Proficient in simulation and HW languages
Should be able to interpret various LRMs and comply with semantics and testcase creation.

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