Job Description:

We are seeking skilled Design Verification (DV) Engineers with 7+ years of experience to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.

You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon.

Job Locations:

Bengaluru / Chennai / Hyderabad

Key Responsibilities
Develop directed and constrained-random testcases
Debug failures and root-cause issues across RTL, testbench, and tools
RTL as well as Gate level simulations
Automate regression flows and improve verification productivity

Required Skills & Qualifications

Technical Skills
Good knowledge of SystemVerilog
Hands-on experience with UVM (Universal Verification Methodology)
Experience with EDA tools (e.g., VCS, Verdi...