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Design Verification engineer/Senior (System Verilog/UVM)

Company

People Profilers

Location

Ho Chi Minh City, Hồ Chí Minh

Posted

June 28, 2026

Position Overview

Job Description:

Job Ref: QV79VR4R

Title: Design Verification Engineer


Location: Onsite in HCM City


Requirements:

4+ years experience with Design Verification


Strong experience with SystemVerilog


Strong experience developing test benches with UVM


Strong experience implementing test cases with UVM


Experience with standard interfaces such as I2C, UART, SPI, AMBA, AHB, USB, etc.


Experience with these interfaces is a bonus: PCIe, UCIe, CXL, Ethernet

Contact: Phuong Le - 0903432692 - [email protected] 

Required Skills:

Design

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