DFT EngineerExperience - 5+yearsLocation- Bangalore/HyderabadExperience with Chip level DFT and Post Silicon debug / analysisUnderstanding of DFT architectures like :scan chain insertion and verificationScan Compression TechniquesJTAGa. ATPG Pattern generationb. ATPG coverage analysisc. Pattern simulation ( both timing/no timing)d. Pattern Retargetinge. Understanding JTAG/IJTAGf. MBIST and Logic BISTProficient in writing SDC constructs for DFT modesProficient in Python, PERL/Shell scriptExcellent hands-on debug skills and problem-solving attitude.Strong Digital design conceptsGenerating scan patterns and coverage statistics for various fault models like :stuck at, IDDQ,Transition faults, JTAG BSDL,pattern generation for Memories (E-fuse etc.)