DFx Micro-Architecture

• Drive technical readiness (TR), that is understand customer requirement and further design relevant DFT/DFD/DFV features. DFT stand for Design for testability (testability from tester), DFD stand for Design for debug (Debug capability in Silicon or customer end ) and DFV stand for Design for validation ( validate effective with simple flow and method )
• Architect and implement DFX strategy, These include provide uarch solution for TAP, Bscan, Scan, MBIST, IO DFX ( leakage, power, loopback ), debug port etc. for test testability and manufacturability.
• Define DFx design methodology and uarch to ensure good coverage ( Scan and functional ) for IP and meet products' DPM requirements
• Overseeing the Scan/ATPG definition, design, verification, and documentation
• Good and close loop communication across function group (Logic, Val, Ckt, SD, HVM ) to ensure a right DFX arch introduce to the IP.
• Perform yield an...