Singapore, Singapore | Posted on 06/13/2024
- PerformATPG pattern generation including SSA /Transition/RSQ Path Delay and IDDQpattern using Siemens Tessen tools
- PerformATPG verification and simulation playback using Synopsys/ Cadence simulator
- StrongAnalytical mindset and simulation debug capabilities to resolve simulationmis-match
- Gooddesign knowledge needed that can help improve the test coverage the lowcoverage of a design
- Deliverhigh quality ATE patterns for production ATE testing
- test pattern support to ATE engineering team for First Proto bring up andfailure analysis in the use of ATPG test and scan/debug features
Requirements - Bachelor degree or equivalent in Electrical orComputer Engineering
- 3 to5 years DFT working experience
- Familiarwith HDL design language
- Goodworking knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell,Perl)