Hands on experience with DFT of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 14nm)
Should have experience in DFT and ATPG activities on SoC designs with expertise in MBIST Planning/Insertion, Partitioning Design for Scan, Scan Insertion, Compression, Wrapper Insertion, ATPG Simulations Expertise in handling Flat/Hierarchical SoC designs Expertise in JTAG, Boundary Scan, STA Constraints creation for DFT modes
Desired Skills and Experience:
B. Tech. / M. Tech. with 5+ years of relevant experience The candidate should be able to work with and lead a team of engineers Should have worked on full chip DFT activities for atleast 2-3 SoC designs Experienced in industry standard tools viz. Mentor/Cadence Knowledge in TCL, Perl scripting is preferable