Job Responsibilities:
1. Responsible for module verification and system verification of SOC digital circuits;
2. Write verification specifications, test plans, and test cases according to the design specifications;
3. Set up the verification platform and environment; debug problems encountered in simulation to improve verification coverage and ensure verification completeness.
Job Requirements:
1. Experience in algorithm-based digital circuit development, with preference given to candidates with experience in PPA (power/performance/area) optimization, complex IP, or ultra-low power circuit design;
2. Proficient in Verilog or SystemVerilog syntax, and skilled in using scripting languages such as C/Tcl/Shell/Perl/Python;
3. Familiar with SDC constraint writing rules, familiar with Netlist ECO processes, proficient in using EDA tools such as VCS, Verdi, DC, Formality, and Spyglass, and understand the use of PT tools or UVM verification methods.