• Develop a thorough understanding of system-level design specifications 

• Verilog RTL Coding, Synthesis, Simulation of the digital IPs 

• Develop advanced verification environment and test-bench components 

• Conduct RTL linting, CDC/RDC checks, and formal verification as part of the sign-off flow 

• Perform synthesis, timing analysis, and work with physical design teams on DFT and timing closure 

• Hardware verification of the digital module using cutting edge FPGA kits 

• Gate level verification of digital IPs 

Essential Qualifications and Experience:  

• Bachelor’s degree of: Electronics Engineering, M.Sc. in Electronics Engineering is a plus