Responsibilities for this position involve working closely with SOC Design, SW/System, and Chipset PE/PM/PdM to validate Digital SOC chip on ATE, SLT and Bench; collaborate with Test Engineering, SLT, and Bench to develop HVM Test Solution. The role is expected from project planning to execution on Digital SOC development. Cross collaboration work is expected with SW, System, Design, Process and Customer Engineering on power and performance related tests for High Volume Manufacturing. The individuals selected for the positions will need to be able to work in a fast paced and dynamic environment and be passionate about delivering quality work.

Experience in Digital SOC development from planning, silicon validation to High Volume Manufacturing phase. Experience in ATE/SLT test coverage, test HW development, data analytics/ statistics, product reliability qualification (ESD/LU, HTOL and Package Qual), ATE System correlation for power a...