Engage in RTL/Digital circuit design, synthesis, and simulation/verification.
Conduct FPGA synthesis and verification processes.
Manage chip integration, algorithm implementation, and interface design.
Generate test patterns.
Qualifications:
More than 3 years of related work experience
Proficiency in ASIC Flow/EDA Tools, including Synthesis DCG, Scan at-speed insertion, LEC, CLP, PrimeTime STA, PTPX, and Low-power flow implementation. Experience in CAD Team is advantageous.
Familiarity with ASIC/FPGA Integration, encompassing ARM CPU architecture, AXI/AHB/VCI Bus arbiter, Clock tree scheme, ASIC/SOC Power optimization flow, and Xilinx FPGA V7 Scale.
Knowledge of high-speed NAND flash specifications and control, or experience in eMMC/UFS IP design, is a plus.
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