Risk assessment of NAND cell reliability, identification of the process/trim/test strategy to bridge the gaps for JEDEC and internal product qualification.

Design experiments to identify and segment the limiting reliability mechanisms impacting NAND quality.

Design high volume electrical experiments (both wafer level and component level) and perform statistical data analysis to validate process/trims solutions required to close reliability gaps.

Update management and provide continuous feedback to process development and product engineers on the NAND reliability status and roadmap to bridge gaps.

Contribute to develop forward looking technology path finding for next NAND generation, including reliability risk assessment and product capability projections, identify innovative design and product features required to meet quality...