Job Description

The candidate will support Place and Route tools, flows, and methodologies used in FPGA silicon design development.

Job Details

• Assist in developing and improving Place and Route flows and tools under the guidance of senior engineers.
• Help maintain existing design flow tools and provide basic end‑user support, including troubleshooting common issues and running regression prior to releasing to production.
• Collaborate with engineers across multiple geographic locations as part of a global team.

Qualifications

• Basic understanding of Place and Route concepts and FPGA or ASIC design flows.
• Familiarity with EDA tools, such as Synopsys Fusion Compiler or Cadence Innovus, through coursework, projects, or initial work experience.
• Programming experience in one or more languages (such as Python, Tcl, or C/C++) and a willingness to continue developing coding skills.