Overview

Number of positions: 3

A person good in Verilog/SystemVerilog based RTL design/verification. Exposure to Xilinx Vivado/Vitis based hardware design and C-language programming is a plus.

Responsibilities

• implementation of IP blocks and their integration on SoC/FPGA devices.
• design, testing, and verification of RISC-V based IP.

Qualifications

Bachelors or higher in a relevant field; experience level can be fresh graduates or professionals. Skills in Verilog/SystemVerilog and exposure to Xilinx toolchains are valued. C-language programming is a plus.

About the role

Both fresh graduates and experienced professionals can apply. Salary will be commensurate with skills/experience. Only short-listed candidates will be contacted. The hired person will get an opportunity to learn and work on leading-edge technologies under the guidance of an experienced team.