Join Ciena as a Frontend ASIC Engineer, focusing on high-speed digital signal processing. Your role will emphasize synthesis and timing analysis to enhance ASIC performance.
Ciena aims to innovate in the world of optical networking, and this position is crucial for executing frontend implementation for DSP-centric ASIC technologies. You will collaborate extensively with various engineering teams to ensure functional integrity. By developing scripts and optimizing workflows, you will contribute to high-quality ASIC designs.
Key Responsibilities:
• Implement frontend designs for assigned ASIC IP subsystems
• Maintain timing constraints for synthesis and integration
• Verify logical equivalence in pre and post-layout stages
• Ensure clock domain crossing validation for ASICS
• Enhance methodologies with custom scripts and tools
Requirements:
• B.Sc. in Electrical or Computer Engineering
• Proficient with ASIC design tools and methodologies
• Understanding ...