Job Description:

Architecture & Design

• Define FPGA architecture for protocol filtering, deep packet inspection, and capture engines.

• Design RTL for hardware accelerators, high-speed bus interfaces, and external memory controllers.

• Implement demodulators and decoders for Bluetooth (LE, Classic) and proprietary protocols.

• Optimize FPGA resources to maximize timing closure, throughput, and clock frequencies.

Leadership & Collaboration

• Lead engineers through the complete FPGA development lifecycle from concept to hardware timing closure.

• Collaborate closely with RF boards, software drivers, and system validation teams.

• Mentor junior and mid-level digital design and FPGA implementation engineers.

• Drive code reviews to maintain high-quality RTL and synthesis standards.

Verif...