Join Infosys as a Memory Layout Design Lead in Vancouver and harness your creativity in cutting-edge memory design. Work closely with teams to develop high-performance layouts.
This position focuses on Compiler and Custom Memory Layout design, requiring over five years of relevant experience. Ideal candidates will excel in FinFET technology, alongside hands-on skills in Cadence Virtuoso and layout optimization. You will play a key role in the integration and performance of our memory architectures.
Key Responsibilities:
• Direct layout design of memory leafcell libraries
• Collaborate with engineers on high-performance memory designs
• Ensure rigorous physical verification including DRC and LVS
• Innovate optimized layout design techniques
• Maintain knowledge on memory architectures and technologies
Requirements:
• Minimum 4 years of IT experience
• Bachelor’s degree or equivalent experience in related field
• Proven experience with FinFET technology