Post-Silicon Memory Validation Staff Engineer

THE ROLE

Processor silicon DDR interface feature enablement, electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring‑up & feature enable, & debugs electrical issues in the memory sub‑system of new processors.

THE PERSON

The person needs to be well self‑motivated for deliveries and innovation, strong technical background on DDR interface, also with good communication skills.

KEY RESPONSIBILITIES

• Provides DDR technical leadership in the development of new test & validation features
• Closely interacts with silicon design (DRAM controller and memory Phy) in test execution & debug, as well as in feature definition for future product generation
• Writes comprehensive electrical & functional test plans for the memory validation of processors
• Executes ele...