As the Manager for NAND Design Rule/Process Integration, you will lead a talented team to support both development and large‑scale production of advanced 3D NAND technologies. This position is essential for producing accurate design‑rule and PDK results, ensuring high quality, and maintaining strict documentation across R&D and production efforts.

Lead the release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews for both R&D and production developments. Own program execution and achievements from kickoff through end‑of‑life. Partner with collaborators across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations. Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions. Collaborate with Yield Improvement, Prod...