Hi,

Opening for Full chip SOC DV requirement with PCIe (Gen 5) and DDR4/DDR5 subsystem experience (10+ yrs)

Job Description for 1 PCIe Req
5 to 8 years of experience in

design verification

in a fast-paced development environment.
Strong understanding of the complete

verification lifecycle , including test planning, testbench development, execution, debug, and coverage closure.
Strong hands-on experience in

SystemVerilog and UVM .
Good working knowledge of

PCIe and AMBA protocols .
Minimum

1 year of hands-on experience in PCIe Gen5 or Gen6

is mandatory.
Proven expertise in developing

UVM testbench environments and verification components

such as drivers, monitors, scoreboards, and agents from scratch.
Self-motivated and result-oriented, with strong

debugging, analytical, and communication skills .

Please share your resume to

jayalakshmi.r2@us...