Our client is expanding their RTL team and is looking for a Lead PCS Design Engineer with strong RTL and architecture background, focused on PCS, FEC and SERDES related Ethernet blocks.
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In this role, you will work in several areas of a RISC V based design for an advanced technology node. The team values vertical engineers who understand the architecture problem and can take it down to RTL implementation.
Location : Barcelona, Spain - Hybrid
Responsibilities:
Design and implement RTL for PCS and FEC related blocks
Work on Ethernet SERDES PHY and controller integration
Translate architecture requirements into Verilog or VHDL implementation
Work with timing constraints and design closure needs
Support block level testing
Collaborate with architecture, verification and p...