Physical Design Engineer – 3 to 10 Years Experience
We are looking for a highly skilled

Physical Design Engineer

with 3 to 10 years of experience in ASIC/SoC physical implementation for advanced technology nodes. The ideal candidate should have strong expertise in full-chip/block-level physical design flow, timing closure, and physical verification methodologies.
Key Responsibilities
Perform end-to-end Physical Design activities including:
Floorplanning
Power Planning
Placement
Clock Tree Synthesis (CTS)
Routing
Timing Closure
Physical Verification
Work on advanced nodes such as 28nm/16nm/7nm/5nm technologies.
Analyze and fix timing, congestion, IR drop, EM, and DRC/LVS issues.
Optimize design for PPA (Power, Performance, Area).
Handle ECO implementation and signoff closure.
Collaborate with RTL, STA, DFT, and verification teams for smooth design convergence.
Ensure high-quality delivery within project timelines.
Deve...