Job SummaryWe are seeking a skilled Physical Design Engineer with approximately 4 years of hands-on experience in the full-chip or block-level physical implementation of ASIC/So C designs. The ideal candidate will have strong expertise in physical design flows, timing closure, and signoff activities for advanced technology nodes.Key ResponsibilitiesPerform block-level and/or full-chip physical design implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and optimizationOwn timing closure across all implementation stages (pre-CTS, post-CTS, post-route)Handle congestion, IR drop, and power optimizationRun and debug DRC, LVS, and physical verification issuesPerform ECO implementation to address timing, power, and functional fixesWork closely with RTL, STA, DFT, and Signoff teams to resolve design issuesAnalyze and fix timing violations (setup, hold, DRV) across multiple modes and cornersSupport signoff checks such as STA, SI, IR/EM, and power analysisCont...