We are seeking a Physical Design Lead to own and drive the end-to-end physical implementation of testchips and high-speed interface subsystems such as DDR/LPDDR PHY, HBM PHY, and UCIe from netlist through tape-out ready GDSII on leading-edge process nodes. This is a technical lead role: candidate is expected to take full ownership of implementation scope, mentor junior PD engineers, define methodology, and drive cross-functional coordination with RTL design, DFT, analog/custom layout, and verification teams. Seniority level to be determined by experience.

Key Responsibilities

• Own end-to-end physical implementation of assigned testchip or high-speed interface subsystem(DDR/LPDDR, HBM, UCIe, or equivalent): floorplanning, power grid design, placement, clock tree synthesis(CTS), routing, and chip finishing through to GDSII stream-out.
• Coordinate timing closure across all functional modes and PVT corners with the dedicated full-chip STAowner; provide...