Responsibilities:

• Drive full-chip and block-level physical implementation, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
• Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation.
• Perform physical verification (DRC/LVS), crosstalk analysis, and EM/IR checks to ensure design reliability and manufacturability.
• Collaborate with front-end design, STA, and power teams to resolve timing, congestion, and design rule issues efficiently.
• Develop and maintain methodology scripts (Tcl, Perl, or Python) to automate and streamline physical design and STA workflows.
• Utilize advanced PnR tools such as Synopsys ICC2/ICC, Fusion Compiler, or Cadence Innovus f...