Experience

3-10 years Experience in Physical Design implementation

Responsibilities

• Responsible to independently handle the execution and delivery of a medium to complex full chip/blocks RTL2GDS implementation
• Played a significant role in multiple tape-outs across technology nodes including sub-2nm

Skill Set

• Full chip/complex block implementation
• IO planning (package i/f, ESD, Multi Voltage), ESD
• Partitioning, Hierarchical flows
• Power estimation, planning and analysis (static and dynamic IR, EM)
• Floor planning, placement & congestion, timing closure, CTS, post CTS flow
• PV: DRC/LVS/ GDS checks
• Schedule recovery, team mentoring, customer interaction
• Exposure/knowledge on Synthesis/STA/DFT/LEC/VCLP
• Proficient in industry standard EDA tool flows (SNPS & CDN)
• Low power implementation, verification.