Are you excited about R&D? An R&D Centre in Munich is looking for an experienced AMS Verification Engineer to work full time in their office (no hybrid working!). International candidates with strong skills in System C, System Verilog, Verilog A will be considered and visa can be provided for an exceptional candidate. A competitive salary package including a bonus will be offered.

In your role you will have the following responsibilities:

System level model development for analog/mixed signal ASIC/IP according to both application and circuit design requirements

Implementation of user cases, fault injection and simulation test bench for analog system design verification

Maintenance and quality assurance for analog system models’ accuracy, scalability and reusability

Work with CAD group to improve the mixed signal verification methodology

Analog/ mixed signal fault modeling and simulation

Requirements

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