We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success.

Key Responsibilities:

• Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs
• Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks
• Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards
• Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Coverage planning, developmen...