Responsibilities

• The research investigates the next generation of Neural Processing Units (NPUs), with particular focus on core micro‑architecture. This spans the frontend (branch prediction, BTB, instruction prefetchers), register files, issue and wake‑up logic, scalar functional units, vector functional units, and tensor units; the backend (TLBs, L1, scratchpads); and the broader cache hierarchies and memory systems that feed them. In parallel, the work explores a new generation of CPUs tailored to the agentic AI era. As agent‑based systems now spend time not only on the GPU/NPU but also on the CPU—handling tool calling, agent‑logic scheduling, context management, and similar tasks—the CPU must become resilient to bursty compute and capable of rapid context switching, without the resource thrashing and limited on‑chip contexts that constrain today's designs (most of which support only 2‑way SMT).

• Investigate and prototype new architectura...