Role Overview
As a RISC-V CPU Architect, you will be responsible for defining the next generation of high-performance, energy-efficient processor cores. You will bridge the gap between architectural intent and RTL implementation, driving the ISA extensions and microarchitectural features that differentiate our silicon. This role requires a deep understanding of pipeline design, memory hierarchy, and the evolving RISC-V ecosystem.
Key Responsibilities Microarchitecture Definition:
Define and document detailed microarchitectural specifications for high-performance RISC-V cores, including fetch units, branch predictors, execution units, and complex memory subsystems. Performance Modelling:
Develop and maintain performance models in C/C++ to explore microarchitecture impact on CPU performance. Performance Analysis:
Utilize techniques like RTL simulation, performance modelling, hardware performance monitor (HPM) to identify bottlenecks in the pipeline and suggest architectura...