Job Description NDescription n: NPrincipal AccountabilitiesN * RTL development for ASIC / FPGA N * Responsible for completion of front end design flow (spec to RTL / Netlist) N * Design, micro architect &do RTL coding, Lint, CDC N * Support existing sustenance designs N * Collaborate with Hardwareboard design engineers for system level designs, Board level block diagram design and validation of hardware, utilizing the Company specified hardware design tools Nn Job Complexity N ● Requires in-depth knowledge and experience N ● Solves complex problems;
takes a new perspective using existing solutions N ● Works independently;
Receives minimal guidance N ● Acts as a resource for colleagues with less experience N ● Represents the level at which career may stabilize for many years or even until retirement N ● Contributes to process improvements N ● Typically resolves problems using existing solutions N ● Provides informal guidance to junior staff N ● Works with minimal guidance NEx...