RTL Design Engineer

Key Responsibilities

• Analyze architectural specifications and define detailed microarchitecture for digital design blocks.
• Develop synthesizable RTL using Verilog/SystemVerilog for IPs, subsystems, and SoC components.
• Create and maintain design documentation, including microarchitecture specifications, interface definitions, and implementation guidelines.
• Collaborate with architecture teams to evaluate design trade-offs and optimize solutions for performance, power, and area (PPA).
• Perform RTL quality checks, including:
• Lint analysis
• CDC (Clock Domain Crossing) checks
• RDC (Reset Domain Crossing) checks
• Synthesis and design rule compliance reviews
• Support functional verification teams by reviewing test plans, debugging simulation failures, and resolving design issues.
• Work closely with RTL integration teams to ensure proper subsystem and SoC...