Hi all,
Modernize Chip Solutions is hiring for the below requirement:
Role: RTL Design Engineer
Experience: 5+years
Location: Bengaluru
Notice Period: Immediate to 15 days
Skills Required:
Strong RTL Design using Verilog/System Verilog
Hands-on Micro-Architecture & RTL Implementation
PCIe and/or CXL (Mandatory)
Knowledge of AXI, CDC, FSMs, Pipeline Design
Experience in RTL-to-GDS flow
Exposure to Spy Glass, Design Compiler/Fusion Compiler preferred
If Interested with the above JD, Please share your resume to sushma.vunnam@