This position involves contributing to an AI evaluation program focused on advanced silicon and chip-design workflows. We are looking for senior digital chip design and verification engineers who can dedicate significant time over the next few months to support this initiative.

Two parallel tracks are available for candidates to apply:

• Track 1: RTL Design Engineer
• Track 2: Design Verification Engineer

Track 1: RTL Design Engineer

• 3, 10 years of experience in digital RTL design
• Strong proficiency in Verilog / SystemVerilog
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols
• Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design
• F...