Senior ASIC DFT Engineer, Silicon

_corporate_fare_ Google _place_ Mountain View, CA, USA

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
+ 8 years of experience with Design for Test (DFT).
+ Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision, etc).
+ Experience with one more more of the following: Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), and Internal Joint Test Action Group (IJTAG) tools and flow.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Sci...