We are seeking a highly experienced Senior Staff CAD Engineer to lead and advance EDA design flows, CAD infrastructure, and signoff methodologies for next-generation semiconductor products. This individual will serve as the technical authority for advanced-node IC design environments, enabling successful development and tapeout of RF, Analog, High-Speed IO, and Digital SoC designs on cutting-edge FinFET technologies.

The ideal candidate will have deep expertise in advanced-node PDK management, Cadence design environments, physical verification, signoff automation, and EDA infrastructure management.

Key Responsibilities

• PDK & Infrastructure Management
• Install, qualify, and maintain advanced foundry PDKs for FinFET technologies (5nm, 3nm, and 2nm).
• Manage EDA infrastructure, compute clusters, license servers, and grid utilization.
• Optimize tool perf...