Job Title: Senior Verification Designer
Experience: 5+ Years
Location: Remote

Overview
Seeking experienced verification engineers to work on advanced AI connectivity and high-performance networking architectures.

Responsibilities:
Own verification strategy and execution for

SoCs/IPs (Switches, NICs)
Build block and system-level verification environments
Develop

UVM/SystemVerilog

testbenches, checkers, and coverage
Drive coverage closure and signoff
Collaborate with RTL, architecture, and software teams
Contribute to verification methodology and infrastructure

Requirements
5+ years in ASIC/FPGA verification ( SystemVerilog, UVM )
Strong experience in networking architectures ( Switches, NICs, SmartNICs )
Knowledge of P acket processing, RDMA, Ethernet, PCIe, MAC
Proven experience with high-performance systems
Formal, emulation, or FPGA experience is a plus
B.Tech/M.Tech/PhD in relevant fie...