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Senior Design Verification Engineer

Company

UST

Location

, penang, malaysia, penang

Posted

June 01, 2026

Position Overview

Responsibilities

  • Will be part of a team that handles Verification for complex IP’s and close the Verification to the challenging milestones.
  • IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation
  • Support in building verification infrastructure at the chip level as per the requirements
  • Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification
  • Working with the team and functional leads; Some interaction with cross functional groups

Qualifications

  • Have experience of digital IP verification with SV/UVM/Formal Verification or new methodology of the industry
  • Good understanding of ASIC verification concepts and techniques and Verilog/System Verilog and UVM
  • It’s a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).
  • It’s also a plus if ...

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