JOB DESCRIPTION

Position: Sr DFT Engineer (Lead)– ATPG & Scan Insertion
Experience:

12–15 Years
Role Overview
We are looking for a

Senior DFT Engineer

with deep expertise in

ATPG and Scan Insertion

to support high‑complexity SoC programs for our semiconductor clients. This role requires strong technical ownership across the DFT lifecycle and the ability to deliver

manufacturing‑ready, high‑quality test solutions

in a fast‑paced, multi‑stakeholder environment.

Key Responsibilities
Lead

DFT definition, implementation, and signoff

for complex SoCs and IPs
Own

Scan Insertion and Scan Compression

strategies aligned with performance, area, and test cost goals
Develop, debug, and optimize

ATPG patterns

(stuck‑at, transition, at‑speed) to achieve high fault coverage
Partner with client engineering teams across

RTL, Synthesis, Physi...